Scaling issues in nanoscale double gate FinFETs with source/drain underlap

In this paper the various scaling issues related to underlap FinFET devices with channel lengths of 30 nm and fin widths of 10 nm have been investigated in detail through device simulations using the Sentaurus TCAD simulation package. The effects of scaling the gate length, the fin thickness, the gate insulator thickness, metal gate thickness and source/drain extension lengths have been examined. The impact of image force effect on the gate leakage is also studied. Quantum mechanical effects which become prominent in the nanometer regime have been included in the simulations for obtaining a realistic picture.