Implementation of unsystematic cyclic codes on DSP 56F8300 hybrid board

In this age of information, there is increasing need not only for speed as well as accuracy in the storage, retrieval, and transmission of data. Error correcting codes are a kind of safety net- the mathematical insurance against the vagaries of an imperfect digital world, due to faulty transmission channel, manmade and non-manmade errors, to recover the original data from the corrupted one. Here the approach is to take the unsystematic variant of cyclic code and its implementation in the Motorola DSP 56F8300 hybrid board. This chip has the luxury of having both microcontroller and digital signal processor characteristics on board. Processor Expert® based IDE was used for this purpose and the implementation has been checked with respect to MATLAB® program based output as well as digital TTL gate based hardware. The unsystematic variant has been chosen to eradicate the necessity of the look up tables as required in case of the systematic cyclic codes and on board it has been checked for (3, 1), (7, 4), (15, 11), (31, 26) and (63, 57) codes.