Low-power sequential circuit using single phase Adiabatic Dynamic Logic

This paper presents implementation of sequential logic circuits by using a novel quasi-static single-phase adiabatic dynamic logic (SPADL). SPADL uses only a single sinusoidal source as supply-clock which ensures lower energy dissipation and also simplifies the clocking management. Moreover SPADL logic substantially decreases transistor overheads with improved driving ability and circuit robustness. In order to demonstrate workability of the newly proposed logic, an adiabatic asynchronous sequential circuit, designed using SPADL logic has been implemented in a TSMC 0.18 ¿m CMOS process. CADENCE simulation shows that SPADL mod-10 counter circuits consume only 25% and 14% energy of single phase clocked adiabatic logic and static CMOS at 100 MHz. Both simulation and measurement results verify the functionality of such logic, making it suitable for implementing energy-aware and performance-efficient sequential circuit.