Title :
Device considerations for ultra-low power analog integrated circuits
Author_Institution :
Silterra USA, San Jose, CA, USA
Abstract :
This paper presents silicon-on-insulator (SOI) enhancement mode dual-gate (DG) n-channel junction-field transistor (DG-nJFET) devices for ultra-low power integrated circuit (IC) design. The increasing chip density along with the demands for mobile computing necessitates the need for ultra-low voltage ICs. However, the advanced standard MOSFET devices and CMOS technologies have several limitations for ultra-low voltage analog operation. And, the JFET devices offer a great potential for such applications. In this paper, the device architecture and performance of enhancement mode SOI DG-nJFETs have been presented. The numerical device simulation results show that the enhancement mode DGnJFETs offer low threshold voltage and an excellent ON/OFF performance at a power supply voltage of 0.5 V required for ultra-low voltage analog ICs.
Keywords :
JFET integrated circuits; field effect analogue integrated circuits; integrated circuit modelling; numerical analysis; ON-OFF performance; chip density; mobile computing; n-channel junction-field transistor; numerical device simulation; silicon-on-insulator enhancement mode dual-gate nJFET; threshold voltage; ultralow power analog integrated circuits; voltage 0.5 V; Analog integrated circuits; CMOS technology; Computer architecture; Integrated circuit technology; MOSFET circuits; Mobile computing; Power integrated circuits; Silicon on insulator technology; Threshold voltage; Transistors; 65 nm silicon on-insulator enhancement DG-nJFETs; devices for low power analog ICs; dual-gate (DG) nJFETs; enhancement nJFETs; junction field-effect transistors (JFET); n-channel JFETs (nJFETs);
Conference_Titel :
Computers and Devices for Communication, 2009. CODEC 2009. 4th International Conference on
Conference_Location :
Kolkata
Print_ISBN :
978-1-4244-5073-2
