Degradation-aware analog design flow for lifetime yield analysis and optimization

As integrated circuit technology scales down continuously, transistor parameters will shift from their nominal values due to process-induced variations and time-dependent degradations. While the former issue contributes directly to the production yield of the fresh circuit, the reliability issue will cause an additional yield loss during the lifetime. Thus the prediction of the circuit´s lifetime yield is highly necessary early in the design phase. Considering both process variation and lifetime degradation together, this paper presents a novel framework to analyze and optimize the lifetime yield value based on worst-case distances using exemplary state of the art reliability simulator and design centering software.