Selectively Grown Short Channel Vertical SI-P MOS Transistor for Future Three Dimensional Self-Aligned Integration

Vertical p-MOS transistors with channel lengths down to 150 nm have been fabricated using selective epitaxial growth (SEG) for the definition of the channel region instead of fine line lithography. Because of self aligned facet growth the channel length and the volume diodes thickness which limits the parasitic bipolar transistor can designed more independently. Thus a short channel p-MOS transistor with a high break-through voltage, an ideal sub-threshold behaviour and a high transconductance was fabricated.