Low-Power, Ultra-Low Capacitance Bipolar Transistor Compatible with Mainstream CMOS

A 10-mask 0.5-¿m process is presented which combines three viable technology modules to achieve very small capacitances in a bipolar NPN transistor, whereas compatibility with mainstream CMOS is maintained. Shallow and deep trenches reduce the collector/base and collector/substrate capacitances by more than 50 %. Straps minimise dimensions of the active region by more than 50 %. Application of the Poly-Ridge Emitter Transistor (PRET) concept strongly reduces both base and emitter areas by 33 and 60 %, respectively. Capacitances are lower than conventional 0.5 ¿m-devices by a factor ranging between 2 and 5, whereas high-frequency capability and CMOS compatibility are maintained.