A CMOS Technology for a Sub-5-ns 3.3-V LVTTL 1-Mbit SRAM

This paper describes a CMOS technology designed for static RAMs and microprocessors operating at 3.3 V. The technology features dual-work-function NFETs and PFETs that achieve 0.22 and 0.18 ¿m minimum channel lengths, respectively. It also includes shallow-trench isolation, nitrided oxide for reliability, self-aligned titanium silicide diffusions and polysilicon, a damascene tungsten local interconnect, up to five levels of fully planarized metallization, and sub-half-micron feature sizes. Access time of less than 5 ns is typical for a 1-Mbit SRAM fabricated in this technology, and 150 MHz clock rate is achieved for a microprocessor.