Feasibility of Multilevel Storage in Flash EEPROM Cells

The analog character of charge storage on a floating gate MOS transistor can be used to store more than one bit of information per non-volatile memory cell. For a given technology and cell design, multilevel charge storage increases the bit density, and potentially reduces the cost per bit. The main problem associated with multilevel storage is the non-zero width of each level, and its dependence on process variations, operating conditions and time. This paper discusses the relative weight of these aspects in Flash EEPROMs. The discussion is illustrated by experimental results on four-level storage in a 0.8¿m Flash EEPROM technology.