Capacitance Modelling of Submicronic MOS Transistor based on On-Chip Measurements

Based on on-chip capacitance measurements, we have modelled MOS transistor gate capacitances consistently with Spice Meyer models. A summary of the On-Chip measurement principle is given together with experimental setup and test chip description. Experimental results obtained with a 1 ¿m channel length MOS transistor demonstrate the limitation of electrical models for short channel devices even with an extracted set of parameters. Mismatches between electrical simulations and experimental data can be explained by a specific behavior of a short depleted channel.