DocumentCode
513814
Title
High Performance 0.3 μm CMOS Technology using I-Line Lithography
Author
Montree, A.H. ; Ansem, W.Gehoel-v. ; Huijten, L.H.M. ; Juffermans, C.A.H. ; De Laat, W. T RM ; Lohmeier, M. ; Manders, B.S. ; Meijer, P.M. ; Paulzen, G.M. ; Roes, R.F.M. ; Webster, M.N. ; Zandbergen, P.
Author_Institution
Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands
fYear
1996
fDate
9-11 Sept. 1996
Firstpage
597
Lastpage
600
Abstract
A 0.3 μn CMOS process with an advanced LOCOS field isolation in combination with optimized I-line photolithography is described. High device performance maintaining low off-state leakage currents were obtained using retrograde well technology in combination with shallow junction drain extension devices. The key process technology is the improved poly linewidth control through the use of BARC without degrading device performance.
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1996. ESSDERC '96. Proceedings of the 26th European
Conference_Location
Bologna, Italy
Print_ISBN
286332196X
Type
conf
Filename
5436142
Link To Document