Title :
Experiments with 0.18 μm SiGe Channel PMOSFETs and P+ Poly-SiGe Gate
Author :
Bouillon, P. ; Skotnicki, T. ; Bodnar, S. ; Morin, C. ; Regolini, J.L. ; Gouagout, P. ; Dollfus, P.
Author_Institution :
France Télécom, CNET Grenoble, BP 98, 38243 Meylan, France, Ph: + 33 76 76 41 67, FAX: + 33 76 76 42 99
Abstract :
This paper presents a high performance 0.18 μm PMOS technology based on the use of lowly doped SiGe channel, aiming at high mobility, together with a P+ Poly-SiGe gate for Vth adjustment. Both features are tested separately and their integration is evaluated. First, a 285 mV shift in ϕms is obtained by incorporating Ge fractions up to 55% in P+ polysilicon gates, which should allow further Vth and Ioff current adjustments. Finally, assuming a constant Ioff current, a 40% gain in the saturation current is demonstrated for 0.18 μm SiGe devices compared to conventional ones.
Conference_Titel :
Solid State Device Research Conference, 1996. ESSDERC '96. Proceedings of the 26th European
Conference_Location :
Bologna, Italy
