DocumentCode
513924
Title
Stacked capacitor cell technology for 16M DRAM using double self-aligned contacts
Author
Fukuumoto, M. ; Naito, Y. ; Matsuyama, K. ; Ogawa, H. ; Matsuoka, K. ; Hori, T. ; Sakai, I. ; Nakao, I. ; Kotani, H. ; Iwasaki, H. ; Inoue, M.
Author_Institution
Semiconductor Research Center, Matsushita Electric Ind. Co., Ltd., Moriguchi, Osaka, Japan
fYear
1990
fDate
10-13 Sept. 1990
Firstpage
461
Lastpage
464
Abstract
This paper describes key technology of a small sized stacked capacitor-cell for 16MDRAM. The main feature of the technology is unique and highly productive double self-aligned contact process for bit line and for storage node, whichl is immune against process fluctuations. The cell made by this process showed desirable characteristics for DRAM operation.
Keywords
Boron; Breakdown voltage; Capacitors; Doping profiles; Geometry; Numerical analysis; Numerical simulation; Random access memory; Shape; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1990. ESSDERC '90. 20th European
Conference_Location
Nottingham, England
Print_ISBN
0750300655
Type
conf
Filename
5436316
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