DocumentCode
513925
Title
Buried stacked capacitor cells for 16M and 64M DRAMS
Author
Dietl, J ; DoThanh, L ; Küsters, K.H. ; Kusztelan, L ; Mulhoff, H M ; Muller, W. ; Stelz, F X
Author_Institution
Siemens AG, Otto-Hahn-Ring 6, 8000 Mÿnchen 83
fYear
1990
fDate
10-13 Sept. 1990
Firstpage
465
Lastpage
468
Abstract
The technology and performance of two trench capacitor cell variants for 16 & 64M DRAM application are assessed. Critical cell leakage mechanisms are determined and means of reducing them further are compared. Trench-transistor separation is shown to be non critical with regard to transistor performance and double channelstop implant technology also allows for further transistor optimisation possibilities.
Keywords
Boron; Breakdown voltage; Capacitors; Doping profiles; Geometry; Numerical analysis; Numerical simulation; Random access memory; Shape; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1990. ESSDERC '90. 20th European
Conference_Location
Nottingham, England
Print_ISBN
0750300655
Type
conf
Filename
5436317
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