Single-transistor latch induced degradation in thin-film SOI MOSFETs: implications for sub-micron SOI MOSFETs

The presence of a parasitic bipolar between the source and drain in high quality thin-film SOI MOSFETs can result in a single transistor latch condition. In this paper, we will present results that indicate that the latch condition results in hot carrier induced degradation and therefore limits the maximum drain voltage that can be used. A simple model for the length dependence is presented indicating the crucial nature of this problem as lengths are scaled down to the sub-micron regime.