Measurement and simulation of degradation effects in high voltage DMOS devices

One of the main constraints for the long-term stability of any kind of integrated circuit technology consists in device degradation. The effect of hot electron induced degradation is a threat to MOSFET reliability when scaling to submicron dimensions. Nevertheless this effect has to be taken into account in high voltage analog MOS circuits as used in telecommunications as well. Various measurements and simulations have been performed in order to improve the behavior of n-channel high voltage DMOS transistors and to analyze the effects responsible for the degradation of these devices.