DocumentCode
514014
Title
A Yield Modelling System for NMOS and CMOS IC
Author
Yie, He ; Yanhui, Shen
Author_Institution
Microelectronics Center, Southeast University, Nanjinig 210018, Nanjing, China
fYear
1989
fDate
11-14 Sept. 1989
Firstpage
210
Lastpage
213
Abstract
In this paper, a multi-level modelling system, which takes into account the statistical fluctuations inherent in the IC manufacturing process, is described. In the modelling system, a reverse statistical simulation method and a yield model expressed in quadratic form are used, which effectively reduces the simulation time in statistical design of integrated circuit and makes it possible to perform an optimum yield design with a low computation cost.
Keywords
CMOS integrated circuits; CMOS process; Circuit simulation; Computational modeling; Fluctuations; Integrated circuit modeling; Integrated circuit yield; MOS devices; Manufacturing processes; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1989. ESSDERC '89. 19th European
Conference_Location
Berlin, Germany
Print_ISBN
0387510001
Type
conf
Filename
5436631
Link To Document