A Bipolar DC Model for Transistors Fabricated in a CMOS Process

an isolated vertical npn transistor fabricated in an n-well CMOS process is described. Characterisitic features of the transistor are examined, particularly in relation to the absence of a buried layer and low well doping. An equivalent circuit is presented to model the structure as a 4-terminal device, which can be implemented in SPICE without modification to the SPICE BJT model. A parameter extraction sequence for the model is detailed and the results of a parameter optimisation for a real device are presented.