DocumentCode
514148
Title
A Self Aligned Contact Process with Improved Surface Planarization
Author
Kusters, K.H. ; Sesselmann, W. ; Melzner, H. ; Friesel, B.
Author_Institution
Siemens AG, Microelectronic Technology Center, Otto-Hahn-Ring 6, D-8000 Mÿnchen 83, FFR. G.
fYear
1988
fDate
13-16 Sept. 1988
Abstract
A new self aligned contact technology has been introduced into a 4Mbit DRAM process. The contact hole is overlapping gate and field oxide. A thin nitride/thin poly-Si/oxide multilayer allows a contact hole etch, which does not significantly affect the oxide isolation of the gate and the field oxide. After acting as etch stop, the poly-Si is changed into oxide by selective oxidation. The new process offers an improved reflow of isolation oxide and contact hole rounding.
Keywords
Anisotropic magnetoresistance; Capacitors; Dielectrics; Nonhomogeneous media; Oxidation; Planarization; Plasma applications; Random access memory; Surface resistance; Wet etching;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1988. ESSDERC '88. 18th European
Conference_Location
Montpellier, France
Print_ISBN
2868830994
Type
conf
Filename
5436966
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