DocumentCode :
514166
Title :
Comparison of ECL Gate Performances using Different Heterojunction Bipolar Transistors Process
Author :
Dangla, J. ; Havond, D.
Author_Institution :
Centre National d´´Etudes des Télécommunications, Laboratoire de Bagneux, 196, rue H. Ravera, F-92220 Bagneux, France
fYear :
1988
fDate :
13-16 Sept. 1988
Abstract :
The switching performance of GaAlAs/GaAs n - p - n Heterojunction Bipolar transistors (HBT) has been investigated for Emitter Coupled Logic (ECL) circuit operation using a CAD model witch has been validated by experimental results. Switching time is discussed in conjunction with layer parameters, design rules, and technological process. The simulation shows the existence of an optimun both for the base thickness and the emitter width. Finally Mesa process give lower switching time than the implanted one.
Keywords :
Circuit simulation; Coupling circuits; Design automation; Gallium arsenide; Heterojunction bipolar transistors; Integrated circuit technology; Laboratories; Logic circuits; Logic design; Logic devices;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Device Research Conference, 1988. ESSDERC '88. 18th European
Conference_Location :
Montpellier, France
Print_ISBN :
2868830994
Type :
conf
Filename :
5436991
Link To Document :
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