Built-in self test design of power switch with clock-gated charge/discharge transistor

It is becoming common to implement header (footer) power switches in low-power system-on-chip. However, the switches are not tested for manufacturing defects in most designs currently. In this study, a novel built-in self test (BIST) solution for power switch is proposed. To accelerate the test of the header (footer) switches, a charge (discharge) transistor is adopted in the proposed BIST circuit and the corresponding charge (discharge) transistor is gated by the test clock. Therefore the number of test patterns, the length of test vectors and the test time are all decreased. Besides, the test responses can be identified easily. If the test responses are all logic-high, the tested switches are fault-free. Or else, the tested switches are faulty. In addition, the structure of the proposed BIST circuit can be scaled freely with the amount of switches. For m switches, it takes m + 2 cycles to locate the faulty switches at worst. Finally, to verify the proposed BIST circuit, the BIST design with 255 header switches is implemented with SMIC 0.18 μm 1P6M logic process. The corresponding area is 0.043 mm². The simulation results show that the BIST circuit can locate the possible manufacturing defects in the switches and discharge transistors within 257 clock cycles. The corresponding consumed power is 2.04 mW when the test frequency is 20 MHz.