DocumentCode
516153
Title
Digital CMOS Sea-of-Gates Core Cells and Master Images
Author
Koopman, R.J.H. ; LLopis, R. Peset ; Kerkhoff, H.G.
Author_Institution
IC-Technol. & Electron. Group, Univ. of Twente, Enschede, Netherlands
Volume
1
fYear
1990
fDate
19-21 Sept. 1990
Firstpage
245
Lastpage
248
Abstract
New digital CMOS sea-of-gates architectures are being developed in order to increase the flexibility and density in generating micro-cells. The key feature of these sea-of-gates architectures is the absence of a row-oriented architecture. This paper presents two newly developed sea-of-gates arrays. In order to investigate the suitability of the developed arrays a multiplier circuit has been designed and a test chip has been realized. The measurement results of this test chip are presented.
Keywords
CMOS logic circuits; logic arrays; logic design; multiplying circuits; digital CMOS sea-of-gates core cell architectures; master images; multiplier circuit design; row-oriented architecture; sea-of-gates arrays; test chip; Application specific integrated circuits; Circuit testing; Integrated circuit interconnections; Integrated circuit measurements; Process design; Routing; Semiconductor device measurement; Shape; Ultra large scale integration; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European
Conference_Location
Grenoble
Print_ISBN
2-86332-087-4
Type
conf
Filename
5467725
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