DocumentCode :
516163
Title :
A 20 MHz, CCITT requirements compatible, Discrete Cosine Transform
Author :
Chaisemartin, P. ; Kritter, S. ; Artieri, A.
Author_Institution :
SGS-Thomson Microelectron., Grenoble, France
Volume :
1
fYear :
1990
fDate :
19-21 Sept. 1990
Firstpage :
197
Lastpage :
200
Abstract :
Recent evolutions in digital video processing and public image transmissions have led to a standard coding method.This method which is the discrete cosine transform has to meet the H261 standard requirements specified by the CCITT. For this purpose, we propose a dedicated processor for the 2 dimensionnal forward or inverse discrete cosine transform (FDCT or IDCT) for 8×8 block size. A double precision mode provides the FDCT and IDCT computation at a data rate of 20 MHz according to CCITT requirements. An optimized mode for specific applications such as video disk storage allows to compute the FDCT and IDCT at a high speed data rate up to 27 MHz. A full custom approach using a double metal 1.2μ CMOS process with an optimized pipe-line architecture has been chosen to fullfill both speed and size constraints.
Keywords :
CMOS integrated circuits; disc storage; discrete cosine transforms; pipeline processing; video coding; CCITT requirement; CMOS process; FDCT computation; H261 standard requirement; IDCT computation; block size; digital video processing; double precision mode; frequency 20 MHz; inverse discrete cosine transform; optimized pipe-line architecture; public image transmission; size 1.2 mum; size constraint; speed constraint; standard coding method; video disk storage; CMOS process; Circuits; Clocks; Computer architecture; Computer interfaces; Concurrent computing; Discrete cosine transforms; Frequency; Image coding; Microelectronics;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European
Conference_Location :
Grenoble
Print_ISBN :
2-86332-087-4
Type :
conf
Filename :
5467739
Link To Document :
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