Circuit Techniques for 1.5-3.6V Battery-Operated 64Mb DRAMs

Author

Nakagome, Y. ; Itoh, K. ; Takeuchi, K. ; Kume, E. ; Tanaka, H. ; Mushya, T. ; Kaga, T. ; Kisu, T. ; Nishida, T. ; Kawamoto, Y. ; Aoki, M.

Author_Institution

Central Res. Lab., Hitachi Ltd., Kokubunji, Japan

Volume

1

fYear

1990

fDate

19-21 Sept. 1990

Firstpage

157

Lastpage

160

Abstract

Novel circuit techniques to achieve wide range of supply voltage (universal-Vcc) for realizing battery-operated DRAMs have been presented. These are: dual voltage limiter enabling scaled MOSFETs to be used for input/output buffers and power supply unit; two-way power supply scheme to realize stable operation at low operating voltage. A 1.5-3.6V 64Mb DRAM has been designed using these techniques. Almost constant RAS access time has been obtained for 1.5-3.6V external power supply voltage. This result implies that the battery operated DRAM is a promising target for the future.

Keywords

DRAM chips; MOS memory circuits; buffer circuits; integrated circuit design; limiters; power supplies to apparatus; battery-operated DRAM design; circuit techniques; constant RAS access time; dual voltage limiter; input-output buffers; power supply voltage; scaled MOSFET; two-way power supply scheme; voltage 1.5 V to 3.6 V; Circuits; Delay effects; Laboratories; MOSFETs; Power supplies; Random access memory; Stress; Switches; Switching converters; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European

Conference_Location

Grenoble

Print_ISBN

2-86332-087-4

Type

conf

Filename

5467757