On-Chip Test Circuitry for a 2 ns Cycle 512Kb CMOS ECL SRAM

On-chip test circuitry which provides 8-bit-deep ECL-level patterns to 12 input pads of a 512Kb CMOS ECL SRAM at cycle times as fast as 1.4 ns has been built in a 0.8¿m CMOS technology with Leff = 0.5¿m. A unique approach for synchronizing the input signals to the chip-select signal in order to provide optimum set-up time and data-valid window is described. Measured results and extensive simulation demonstrate the stability of the on-chip test circuitry for cycle times of 1.4 ns to 50 ns.