• DocumentCode
    516181
  • Title

    A Pipelined 330 MHz Multiplier

  • Author

    Schmitt-Landsiedel, D. ; Noll, T.G. ; Klar, H. ; Enders, G.

  • fYear
    1985
  • fDate
    16-18 Sept. 1985
  • Firstpage
    9
  • Lastpage
    12
  • Abstract
    An 8 × 8 bit NMOS multiplier test chip for image processing systems has been realized on the basis of a newly designed carry save adder cell, a multiplication rate of 3.3 108 1/sec (fc = 330 MHz) being achieved.
  • Keywords
    Clocks; Delay; Frequency; Image processing; MOS devices; Pipeline processing; Power dissipation; Registers; Throughput; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1985. ESSCIRC '85. 11th European
  • Conference_Location
    Toulouse, France
  • Type

    conf

  • Filename
    5467762
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516181