• DocumentCode
    516187
  • Title

    JTAG SRAM Tester Chip

  • Author

    Kritter, Sylvain

  • Author_Institution
    SGS THOMSON MICROELECTRONICS, Central R&D - CAD and Integrated systems, GRENOBLE - FRANCE
  • Volume
    1
  • fYear
    1991
  • fDate
    11-13 Sept. 1991
  • Firstpage
    221
  • Lastpage
    224
  • Abstract
    This paper describes a chip dedicated to test static RAM arrays on pc board. This chip is fully JTAG(1149.1) compatible, and has self-test capability. This is a real versatile product, in accordance to the Hierarchical Self-Test Concept. The design has been made with synthesis tools for the core and hard-macro for the Boundary-Scan Registers.
  • Keywords
    Automatic testing; Built-in self-test; Impedance; Macrocell networks; Neodymium; Pins; Random access memory; Read-write memory; Registers; System testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1991. ESSCIRC '91. Proceedings - Seventeenth European
  • Conference_Location
    Milan, Italy
  • Type

    conf

  • Filename
    5467768
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516187