Title :
JTAG SRAM Tester Chip
Author :
Kritter, Sylvain
Author_Institution :
SGS THOMSON MICROELECTRONICS, Central R&D - CAD and Integrated systems, GRENOBLE - FRANCE
Abstract :
This paper describes a chip dedicated to test static RAM arrays on pc board. This chip is fully JTAG(1149.1) compatible, and has self-test capability. This is a real versatile product, in accordance to the Hierarchical Self-Test Concept. The design has been made with synthesis tools for the core and hard-macro for the Boundary-Scan Registers.
Keywords :
Automatic testing; Built-in self-test; Impedance; Macrocell networks; Neodymium; Pins; Random access memory; Read-write memory; Registers; System testing;
Conference_Titel :
Solid-State Circuits Conference, 1991. ESSCIRC '91. Proceedings - Seventeenth European
Conference_Location :
Milan, Italy
