DocumentCode :
516189
Title :
A Flexible High Perfomance Serial Radix-2 FFT Butterfly Arithmetic Unit
Author :
Greiner, Alain ; Kara-Terki, C. ; Mehrez, H. ; Neguez, G.
Author_Institution :
Université Pierre et Marie Curie, (Paris VI)
fYear :
1985
fDate :
16-18 Sept. 1985
Firstpage :
25
Lastpage :
28
Abstract :
This paper describes the architecture and the design of a high performance single chip Radix-2 FFT Butterfly. The architecture is optimized to a very efficient bit-serial data processing and to a pipeline-parallel hardware structures. The design is based on a standard cell approach including LSSD test capabilities. The circuit has been fabricated at CNET (centre of Meylan Grenoble France) as part of French MPC with 4.5¿ NMOS technology. It contains about 6000 transistors. The chip area is 20 mm2. The circuit uses dynamic logic controlled by a nonoverlapping two phese clock up to 20Mhz. Power dissipation is about 900mw. The chip performs up to 10.5 millions 16×12 bits real multiplications/s.
Keywords :
Adders; Arithmetic; Circuits; Computer architecture; Hardware; Pipeline processing; Signal processing; Tellurium; Testing; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1985. ESSCIRC '85. 11th European
Conference_Location :
Toulouse, France
Type :
conf
Filename :
5467770
Link To Document :
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