DocumentCode
516200
Title
A High-Speed On-Chip ECC System Using Modified Hamming Code
Author
Fifield, John A.
Author_Institution
Gen. Technol. Div., IBM, Essex Junction, VT, USA
Volume
1
fYear
1990
fDate
19-21 Sept. 1990
Firstpage
265
Lastpage
268
Abstract
It has been shown that significant improvements to reliability and yield [1] can be attained with Error Correction Code (ECC) systems on DRAM chips. Placement of ECC systems on DRAM chips poses many practical problems, among which are increased access time and chip size. Described is a self-contained and self-timed on-chip ECC system imbedded in a high-speed 16-Mbit DRAM chip [2].
Keywords
DRAM chips; Hamming codes; error correction codes; integrated circuit reliability; DRAM chips; access time; chip size; error correction code; high-speed on-chip ECC system; modified Hamming code; self-contained on-chip system; self-timed on-chip system; Decoding; Delay; Error correction; Error correction codes; Logic design; Random access memory; Registers; System-on-a-chip; Testing; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European
Conference_Location
Grenoble
Print_ISBN
2-86332-087-4
Type
conf
Filename
5467781
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