VLSI – tailored Architectures for Multiplication modulo (2n + 1)

This paper describes VLSI architectures for multiplication modulo p, where p is a Fermat prime. With increasing p, ROM based methods become unattractive for integration due to excessive memory requirements. Two new methods are discussed and compared to ROM implementations with regard to their speed/complexity behaviour. The first method is based on a (n + 1) x (n + 1) bit array multiplier, the second on carry-save addition, both of which allow very high throughputs in pipelined implementations. While the former is very convenient for CAD environments providing a pipelined multiplier macro cell generator, the latter is well-suited to full custom implementation.