Porting of a CMOS VLSI Chip from 2.5 Micron to 1.75 Micron Design Rules

The porting, or updating of a 2.5 micron CMOS VLSI design into 1.75 micron design rules has been completed. This porting involves three major undertakings: (1) reduction of all feature sizes in accordance to the new design rules, (2) simulation at the transistor level of the 1.75 micron circuit behavior and (3) incorporation of several new architectural features in the original topology. Despite the extent of logic changes the resulting design was completed in an extremely short period of time. This paper describes a process by which this and other VLSI designs which require state of the art performance can be transformed into a new generation of design rules in a prompt and efficient manner.