Title :
A 16Ã\x9716 bits Multiplier in 0.5μm CMOS technology
Author :
Belleville, M. ; Bisotto, S. ; Bruel, M. ; Jaffard, C. ; Lerme, M. ; Guegan, G. ; Guerin, M.
Author_Institution :
DTA LETI. CENG. BP85X 38041 Grenoble CEDEX. FRANCE
Abstract :
A 16 × 16 bits Multiplier has been achieved using a 0.5 μm double metal CMOS technology. This function is made of 8340 transistors and has an active area of 1.04 mm2. At 3.3 V, the typical multiplication time is about 7.5 ns, while the fastest one achieved is 6.8 ns. The multiplier is based on Booth´s algorithm and has a special final adder with an arborescent carry propagation.
Keywords :
Architecture; Buildings; CMOS technology; Clocks; Communication channels; Communication system control; Correlators; Digital arithmetic; Ring oscillators; Spread spectrum communication;
Conference_Titel :
Solid-State Circuits Conference, 1991. ESSCIRC '91. Proceedings - Seventeenth European
Conference_Location :
Milan, Italy
