A New Architecture for an Automatic Generation of Fast Pipelined Adders

This paper describes a compact VLSI implementation of fast pipelined adders. A new architecture is presented. Although the speed achieved is lineary proportionnai to o(n), it is faster than if it would be proportional to o(logn) (n equals to the number of bits). A new design strategy has been used to speed up the algorithm. In addition, the whole set of blocks has been designed in order to allow an automatic generation of any size of adders.