DocumentCode
516245
Title
A Systolic Processor for a Digital Video Matrix Operator
Author
Carlac´h, J-C ; Sicre, J-L
Author_Institution
C.C.E.T.T. - rue du Clos Courtel 35510 Cesson-Sevigné -FRANCE
fYear
1984
fDate
0-0 Sept. 1984
Firstpage
39
Lastpage
42
Abstract
The proposed VLSI circuit performs the reverse matrix transformation of the luminance and color difference eight bit coded video signals into RGB signals. The chip is composed of 3 processors each one performing the linear function XA+YB+ZC. Each processor is a systolic array based on the Baugh-Wooley two´s complement parallel multiplication algorithm. The chip has been design in order to support a 18 MHz maximum clock frequency in a 3.15 micron NMOS technology, it achieves a performance figure of merit of 9.5 10 T.Hz.mm-2.
Keywords
Character recognition; Circuits; Design methodology; Graphics; Image coding; Large scale integration; Logic devices; Microprocessors; Optical character recognition software; Text analysis; Digital TV; Systolic architecture; VLSI; matrix multiplication;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1984. ESSCIRC '84. Tenth European
Conference_Location
Edinburgh, UK
Type
conf
Filename
5467838
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