• DocumentCode
    516246
  • Title

    A Pipelined Digital Filter Chip with a Throughput Rate of 100 Mbit/s

  • Author

    Zehner, B. ; Kaschte, W.

  • fYear
    1984
  • fDate
    0-0 Sept. 1984
  • Firstpage
    47
  • Lastpage
    50
  • Abstract
    A digital lowpass filter for an image coding and processing system is described. To achieve the high throughput rate (up to 100 Mbit/s) a pipeline-organization had to be used. The mapping of the filter function to a regular pipeline configuration in bit-slice technique is explained. The circuit was implemented in a standard 2 ¿m NMOS-technique. The 3.2×1.7 mm2 chip needs 3500 transistors and consumes 250 mW.
  • Keywords
    Circuits; Delay; Digital filters; Equations; Hardware; Image coding; Interpolation; Pipeline processing; Standards organizations; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1984. ESSCIRC '84. Tenth European
  • Conference_Location
    Edinburgh, UK
  • Type

    conf

  • Filename
    5467839
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516246