Title :
A Monolithic Impedance Buffer, with a Compatible JFET-CMOS Technology
Author :
Sansen, W. ; Das, C. ; Callewaert, L.
Author_Institution :
Kath. Univ. Leuven, Elektrotechniek, 94 K. Mercierlaan, 3030 Heverlee
Abstract :
An integrated impedance buffer for microelectrodes has been designed. The circuit exhibits a low input capacitance (0.2 pF), a high driving capability and a low power consumption (750 ¿W). The circuit has been implemented in a 5 ¿m p-well CMOS technology with double implanted p-JFET-transistors for low noise performance (90 nV/VHz at 10 Hz).
Keywords :
Bonding; CMOS technology; Capacitance; Circuit noise; Energy consumption; Impedance; Integrated circuit technology; MOSFETs; Microelectrodes; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1984. ESSCIRC '84. Tenth European
Conference_Location :
Edinburgh, UK
