Title :
Design of SCD Checkers based on Analytical Fault Hypotheses
Author :
Jansch, I. ; Courtois, B.
Author_Institution :
IMAG/TIM3 - Institut National et Polytechnique de Grenoble, BP 53 - 38041 GRENOBLE CEDEX - FRANCE
Abstract :
This paper deals with the design of the largest class of checkers - the Strongly Code Disjoint (SCD) checkers - that may be devised such that a combinational system composed of a functional part and a SCD checker achieves the TSC goal. The definition and properties of SCD checker are given. The design of a SCD checker cell is analysed, based on low-level fault hypotheses. Some comments about cells interconnection introduce the idea of a checker cell library.
Keywords :
Circuit faults; Circuit synthesis; Circuit topology; Integrated circuit interconnections; Integrated circuit modeling; Libraries; Logic circuits; Redundancy; Space technology; Test pattern generators;
Conference_Titel :
Solid-State Circuits Conference, 1984. ESSCIRC '84. Tenth European
Conference_Location :
Edinburgh, UK
