Experimental Investigation of the Minimum Signal of DRAM Cells for Reliable Operation of Sense Amplifiers

The sensitivity of a DRAM sense amplifier, generally consisting of cross-coupled pairs of CMOS transistors is limited by mismatches disturbing the circuit symmetry. The minimum cell signal which is correctly sensed due to process tolerances by a sense amplifier is an important quantity, but extremely difficult to measure. We present such measurements in this paper. On this basis we estimate the cell capacitance necessary for a reliable operation of the DRAM. Moreover we use the sense amplifier on our test structure as a monitor to evaluate the above-mentioned process tolerances. For fast sense amplifier operation and short access times, a large initial sense signal is required. We measure how the minimum sense signal is affected by different sense amplifier trigger pulse shapes and sequences. High density DRAMs with fast access times can only be realized, when all these factors are well-optimized.