• DocumentCode
    516332
  • Title

    TOPOLOGIZER: An Expert System Translator of Transistor Connectivity to Symbolic Cell Layout

  • Author

    Kollaritsch, P.W. ; Weste, N.H.E.

  • Author_Institution
    AT&T Bell Laboratories
  • fYear
    1984
  • fDate
    0-0 Sept. 1984
  • Firstpage
    175
  • Lastpage
    178
  • Abstract
    TOPOLOGIZER is an expert system for the design of CMOS cells. It automatically generates a symbolic layout given a transistor connection list and a description of the boundary assignment of external cell connections. As part of an overall approach to silicon compilation it uses expert designer specified heuristics to perform the difficult task of converting a structural description (schematic) into a physical description that maintains some notion of structured layout principles.
  • Keywords
    Assembly systems; Counting circuits; Design methodology; Expert systems; Integrated circuit layout; Libraries; Productivity; Programmable logic arrays; Read only memory; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1984. ESSCIRC '84. Tenth European
  • Conference_Location
    Edinburgh, UK
  • Type

    conf

  • Filename
    5467937
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516332