High Speed GaAs IC´s Design using BDCFL Logic

High speed and large scale system applications are requiring greater speed and integration with very low power dissipation. In order to meet such needs, GaAs Buffered Direct Coupled Fet Logic (BDCFL) was used for IC´s design. The BDCFL basic cell, equivalent to an inverter, consists of two pairs of two enhancement and depletion mode MESFET. This logic, derived from DCFL family, is characterized by low component count for a given logic function and requires only single power supply. We present here a design methodology used for high speed digital circuits where the product Pwd.¿pd was well optimized (Pwd is the power dissipation, ¿pd is the propagation delay). The application of this methodology allows the design of fast communication integrated circuits. Performances of two circuits used in multi-gigabit per second applications are described and Comparison of DCFL and BDCFL exclusive-or results are also presented.