• DocumentCode
    516346
  • Title

    High Speed 2um-gate CMOS Gate Arrays up to 10K-gates

  • Author

    Ichinose, K.

  • Author_Institution
    Gate Array Eng. Dept. TOSHIBA. 72, Horicawa-Cho, Saiwai-Ku, Kawasaki, Japan
  • fYear
    1984
  • fDate
    0-0 Sept. 1984
  • Firstpage
    188
  • Lastpage
    192
  • Abstract
    This paper descrives the current status of the high performance CMOS gate arrays, (1) a 2u-gate CMOS gate array series which has TTL speed and is available in the market, and (2) a sub-nanosecond 8K-gate CMOS/SOS gate array which is developed by using sub-2um design rule and cmpetes with ECL gate arrays.
  • Keywords
    CMOS process; Circuit optimization; Costs; Delay effects; Dry etching; Integrated circuit interconnections; Libraries; Logic functions; Macrocell networks; Planarization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1984. ESSCIRC '84. Tenth European
  • Conference_Location
    Edinburgh, UK
  • Type

    conf

  • Filename
    5467953
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516346