• DocumentCode
    516352
  • Title

    A Design Methodology for Compact Integration of Wave Digital Filters

  • Author

    Van Ginderdeuren, J. ; De Man, H. ; Catthoor, F. ; Beckers, S.

  • Author_Institution
    ESAT Laboratory, Katholieke Universiteit, Leuven, Heveree, Belgium
  • fYear
    1984
  • fDate
    0-0 Sept. 1984
  • Firstpage
    210
  • Lastpage
    213
  • Abstract
    A top-down methodology for custom integration of Wave Digital filters is discussed. The design is supported by a CAD toolbox, which starts from filter specifications, uses a bit serial architecture and results in dense layout. This is demonstrated by a 3rd order elliptical filter chip, which works at a sampling rate of 312 Khz. The area is 1.8mm2 in 6¿m NMOS technology. As a result of scaling, pole-zero areas of 0.2mm2 can be expected for 3¿m technology.
  • Keywords
    Arithmetic; Delay; Design methodology; Digital filters; Hardware; Lattices; Limit-cycles; Sampling methods; Semiconductor device measurement; Shift registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1984. ESSCIRC '84. Tenth European
  • Conference_Location
    Edinburgh, UK
  • Type

    conf

  • Filename
    5467964
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=516352