Current versus Voltage Testing of Bridging Defects in a Dual Port Memory Cell

In order to compare current and logic testing of a static memory cell in the presence of bridging defects, an electrical model for the defective cell is used. The SPICE parameters for the cell have been extracted from the layout and process information. All the extracted bridges are shown to be quiescent current testable. However, for a large percentage of the defects, the logic (voltage) testability cannot be guaranteed. The results are generalized to static memory cell layouts based in four transistors and single or multiple port accesses.