A 125 MHz Monolithic Transceiver Interface for Fiber Distributed Data Interface

A single chip FDDI transceiver is presented. A crystal based dual PLL locks to 125 Mb/s NRZI data and captures them. The receiver jitter tolerance is 6.1 nS. The transmitter converts parallel data into serial data by a PLL generated 125 MHz clock. The high level integration and robust asynchronous operation are achieved. This transceiver operates at a single 5 V supply and dissipates 1.2 W.