A Top-Down VHDL Interface to the Genesil Silicon Compilation System

Genesil was embedded into a VHDL environment in order to support early tradeoffs between ASICs, standard parts and software. A common front end is used to create RTL chip models in VHDL and to drive Genesil. The VHDL-Genesil interface supports use of multiple models with increasing detail and timing back-annotation. Examples are reported of automatically generated VHDL models.