A Very Low-Noise Instrumentation Amplifier using a Standard CMOS Process for Digital Chips

Author

Bardyn, Jean-Paul ; Kaiser, Andreas ; Stefanelli, Bruno

Author_Institution

Inst. Super. d´´Electron. du Nord, Lille, France

Volume

1

fYear

1990

fDate

19-21 Sept. 1990

Firstpage

29

Lastpage

32

Abstract

New design concepts have been applied to a CMOS continuous-time fully differential charge amplifier using parasitic lateral bipolar transistors. Processed in a standard 3 microns P-Well CMOS technology, this circuit combines a very low input noise voltage (3.5nV/jHz @700Hz) with a low input capacitance (<;10pF), high CMRR and PSRR and 50Ω compatible outputs. It can be considered as a good competitor to hybrid JFET high input impedance low-noise preamplifiers.

Keywords

CMOS analogue integrated circuits; CMOS digital integrated circuits; UHF integrated circuits; bipolar analogue integrated circuits; instrumentation amplifiers; low noise amplifiers; CMOS continuous-time fully differential charge amplifier design; CMRR; PSRR; digital chips; parasitic lateral bipolar transistor; size 3 micron; standard CMOS process; standard P-well CMOS technology; very low-noise instrumentation amplifier; Bipolar transistors; CMOS process; CMOS technology; Circuit noise; Differential amplifiers; Impedance; Instruments; Low voltage; Low-noise amplifiers; Parasitic capacitance;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1990. ESSCIRC '90. Sixteenth European

Conference_Location

Grenoble

Print_ISBN

2-86332-087-4

Type

conf

Filename

5467999