Practical Design Techniques for 16-Bit CMOS A/D Delta-Sigma Converter

The purpose of this paper is to show the impact of design details on the performances of a Second Order Single Loop Delta-Sigma A/D CMOS converter, specified for 16 bit resolution and 15 bit linearity in the 0-4 kHz band with 2 MHz clock frequency, taking into account +/- 3 ¿ dispersion due to process variations. Effect of MOS transistors noise, aliasing mechanisms and influence of crosstalks on quantization noise-shaping are analysed. Techniques used to improve dynamic range, to reduce electronic noise and to achieve a good shaping of quantization noise are discussed. Results from two practical realizations¹ which use the same Sigma-Delta structure, the same 2-¿m 5-V CMOS process, but which respectively do not include and include above techniques, are compared.