DocumentCode :
516416
Title :
A 60uA Standby Power 32k Ã\x97 8 Pseudo-Static RAM
Author :
Komuro, T. ; Kuwabara, S. ; Inagaki, Y. ; Kawachi, T. ; Tameda, M. ; Fukuda, T. ; Tsujide, T.
Author_Institution :
NEC Corp., Kawasaki, Japan.
fYear :
1985
fDate :
16-18 Sept. 1985
Firstpage :
147
Lastpage :
151
Abstract :
Standby power of a 32k × 8 pseudo-static RAM has been reduced to 60uA using an expanded internal refresh interval, a reduced oscillating frequency by a back bias generator, and other power saving circuits.
Keywords :
CMOS process; Circuits; DRAM chips; Decoding; Energy consumption; Frequency; National electric code; Oscillators; Random access memory; Read-write memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 1985. ESSCIRC '85. 11th European
Conference_Location :
Toulouse, France
Type :
conf
Filename :
5468045
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=516416
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