Title :
Experimental 8K Bit High Performance Static Bipolar RAM
Author_Institution :
IBM GENERAL TECHNOLOGY DIVISION, ESSEX JUNCTION, VERMONT 05452, TELEPHONE: 802-769-6259
Abstract :
AN EXPERIMENTAL 8K BIT, HIGH PERFORMANCE, STATIC BIPOLAR RAM HAS BEEN DESIGNED AND FABRICATED IN TRENCH ISOLATION TECHNOLOGY. A NOMINAL ACCESS TIME OF 6 NS WAS DEMONSTRATED FOR SATURATED AND SCHOTTKY BARRIER DIODE (SBD) CLAMPED VERSIONS OF THE MULTI-EMITTER COMPLEMENTARY TRANSISTOR SWITCH (CTS) CELL; AND A PREDICTED WORD LINE RECOVERY PROBLEM FOR THE SATURATED VERSION WAS VERIFIED BY HARDWARE TESTING. THE DESIGN HAS BEEN EXTRAPOLATED TO A 40K BIT ARRAY WITH SIMILAR PERFORMANCE.
Keywords :
Hardware; Isolation technology; Read-write memory; Schottky barriers; Schottky diodes; Semiconductor process modeling; Switches; Telephony; Testing; Time measurement;
Conference_Titel :
Solid-State Circuits Conference, 1985. ESSCIRC '85. 11th European
Conference_Location :
Toulouse, France
