Title :
A 5V-0nly 256K CMOS EEPROM using Barrier Height Lowering Technique
Author :
Tsujimotq, Jun-ichi ; Miyamoto, Jun-ichi ; Matsukawa, Naohiro ; Shinada, Kazuyoshi ; Morita, Shigeru ; Nozawa, Hiroshi ; Iizuk, Tetsuya
Author_Institution :
Semiconductor Device Engineering Lab., Toshiba Corporation, Kawasaki, 210 Japan.
Abstract :
A 256k (32k × 8b) 5V-only EEPROM with high-density structure cell has been developed. The EEPROM, offering typically 150ns address access time, 80mW active, and 1¿W standby power dissipation, was successfully fabricated by a single-polysilicon and single metal CMOS process with a 1.2 ¿m photo lithography.
Keywords :
CMOS logic circuits; Clocks; EPROM; Fabrication; Nonvolatile memory; Pulse generation; Signal generators; Timing; Tunneling; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1985. ESSCIRC '85. 11th European
Conference_Location :
Toulouse, France
